Why Is Only One Memory Bank Accessed Per Read or Write Operation?

💡 The Answer

• A memory bank is a logical unit of storage that is hardware-dependent.
• In SDRAM, a bank consists of multiple rows and columns of storage units.
• During a single read or write operation, only one bank is accessed.
• This design limits the number of bits involved to the memory bus width.
• The bus width equals the number of bits in a column or row per bank per chip.